The present invention relates to a video pickup device which is driven by digital-processing a luminance signal and a color difference signal.
In recent years, the propagation rate of home video cameras has increased rapidly. The reasons for this are 1) compactness/light weight, 2) low cost, 3) improvement of characteristics such as high image quality, and 4) improvement of usability due to the development of a movie in which a VTR (Video Tape Recorder) unit and a camera unit are integrated. And it could be noted that 1) a solid state image sensor and 2) rationalization of signal processing have greatly contributed to realization these characteristics.
Generally, solid state image pick-up devices have many characterisitics such as compactness/light weight, high reliability, etc. At the beginning of development, those devices were inferior to camera tubes in their production cost, sensitivity and resolution, etc. With rapid development of semiconductor technology, the solid state video camera has exceeded the camera tubes in the above-mentioned qualities, as well as in production cost and performance. At present, almost all home video cameras adopt the solid state video camera. The history of development of video cameras hitherto made is disclosed in Proceedings of The institute of Television Engineers of Japan, Vol. No. 11 (1987), pp. 983-990.
On the other hand, the signal processing circuit intended to improve signal processing and also to be designed in an IC for the purpose of realizing its compactness, low cost and high performance. As a result, the improved signal processing circuit coupled with above solid state camera has realized the high quality, drastic compactness/light weight and low cost of the home video cameras. However, the analog signal processing system adopted hitherto has a certain limit in further rationalizing the signal processing. In the future, a digital signal processing system, which has the following features, will become the most prevalent signal processing system.
1) It permits a filter which is a bulky component to be integrated in an IC with high accuracy.
2) It can be designed within a single chip by incorporating A/D and D/A converters.
3) It can be designed sufficiently considering deterioration of S/N due to rounding error of calculation thereby to easily realize the signal processing circuit with high S/N ratio.
An example of the signal processing in such a video camera is disclosed in Japanese Patent Publication No. 63-45153.
FIG. 1 a block diagram of the video camera in which the conventional analog signal processing unit is designed in a digital system.
In FIG. 1, in response to an input optical signal, a sensor 1 produces an analog pixel signal 12, for each horizontal read scanning period, which is synchronous with a read clock frequency (hereinafter referred to as a sensor clock) and consisting of alternately repeated different color signals. The operation of the sensor 1 is controlled by the control signal sent from the sensor driving timing generating circuit (hereinafter abbreviated to TG).
The analog pixel signal 12 is A/D converted by an analog/digital converter (hereinafter abbreviated to A/D) to provide a digital pixel signal 13. A digital signal processing circuit 3, when it receives the digital pixel signal 13, a synchronization (sync) signal 20 and a control signal 23 from a synchronization signal generating circuit (hereinafter abbreviated to SSG) and the control signal 18 from TG 5, produces a luminance signal 14 and a color signal 15 supplemented with the sync signal 20, respectively. These signals 14 and 15 are D/A converted by a digital/analog converter (abbreviated to D/A) to provide an analog luminance signal 16 and an analog color signal 17 supplemented with the sync signal 20, respectively.
An explanation will be given of the control signal 18 generated by TG 5 and the sync signal 20 and the control signal 23 generated by SSG 8. First, SSG 8, when the signal 60 at a frequency of n.multidot.fsc is supplied as a clock from an oscillator 61 with an oscillation frequency of n.multidot.fsc (n: an integer; and fsc: the frequency of a color subcarrier), produces a horizontal sync signal (hereinafter referred to as CHD) and a vertical sync signal (hereinafter referred to as VD) which are necessary to generate a sensor driving signal; these two signals 19 are supplied to TG 5. In response to the signal fs from an oscillator 51 and CHD, TG 5 produces a sensor clock fs. On the other hand, in response to the clock signal at nfsc, SSG 8 produces synchronization (sync) signals 20 such as a composite sync signal (CSYNC), a composite blanking signal (CBLK), a burst flag signal (BF), etc. The digital signal processing circuit 3, in response to the sensor clock nfsc, produces the luminance signal and a color difference signal supplemented with the sync signals 20 to provide the luminance signal 14 and the color signal 15 (which is further modulated by the control signal 23), respectively. The art related to the system described above is disclosed in Japanese Patent Publication No. 63-45153.
There are many problems to be solved in digitizing the signal processing in the video camera provided with a CCD sensor, which is the sensor (solid state image pick-up device) in the prior art shown in FIG. 1. One problem is digitizing the encoder for a color signal.
The present CCD sensor adopts several values as the number of horizontal pixels. Since the horizontal scanning period is fixed, there are different frequencies of horizontal pixel read clock (sensor clock) corresponding to the number of pixels. For example, the sensor clock frequency (fs) for an NTSC color television system includes the values of 9.5 MHz, 12.7 MHz, 14.3 MHz, etc. Generally, the signal processing in the digital camera is desired to be performed in a processing synchronous with the sensor clock because of its easiness and merit of small-sized circuit. Now it should be noted that the signal processing in the encoder must be done with the clock n (n : 3 or 4) times as large as fsc. Therefore, if in digitizing all the signal processings in a camera, the relation fs=n.multidot.fsc (n=3, 4, 6, 8, etc.) is not satisfied (the phase of a high clock is not fixed for), jitter of (n.multidot.fs).sup.-1 is generated to transfer the data to the encoder. Now if n=4, the jitter is EQU NTSC : (4fsc).sup.-1 =70 ns, and EQU PAL : (4fsc).sup.-1 =56 ns.
The value of jitter permitted for the color signal is 35 ns or less so that it is apparent that the above jitter are not permitted. It was found that n must be 8 or greater in order to limit within the permitted value. However, actually, the signal processing based on the oscillation at 8 fsc (NTSC : 28.6 MHz, PAL : 35.44 MHz) suffers from the following defects:
1) the oscillation is likely to be unstable to require the strict specifications for an oscillator. The power consumption of the oscillator is doubled, and
2) the speed for a gate used in an encoder circuit is required to be twice as high as before so that the strict specifications are required for components. The power consumption for the encoder circuit is increased. For this reason, actually, the signal processing is desired to be done at the clock at 4 fsc or less. Incidentally, digitizing the encoder is not referred to in the above Japanese Patent Application No. 63-45153.
Further, the prior art shown in FIG. 1 also has the following defect. In converting the signal processing system in the video camera from an analog system to a digital system, no consideration regarding the synchronization of a luminance signal with a sync signal when the luminance signal is supplemented with the sync signal is made although the luminance signal is synchronous with the sensor clock fs and the sync signals such as CSYNC are synchronous with n.multidot.fsc.
FIG. 2 is a timing chart showing the relationship between the sensor clock fs, and CSYNC before it is added to the luminnance signal and CSYNC after it has been added thereto. As seen from FIG. 2, if the rising edge 104 of the sensor clock 101 has the same timing as the falling edge 106 of CSYNC, CSYNC is latched at the rising edge 104 so that it remains unvaried and the waveform 102 after is later added to the luminance signal; on the other hand, CSYNC is latched not at the rising edge 104 but the rising edge 105, and SYNC is later added to the luminance signal having the waveform 103. In this case, the timing difference between CSYNC 102 and CSYNC 103 in their falling edge is 1/fs. For example, the number of sensor clock in the horizontal period of the sensor is 550, 1/fs=1H/550=115 ns. Such a large timing difference will produce jitter in the output image which is visible to human eyes.
Further, since the horizontal read clock frequency in the sensor for TG5 is fixed at a certain value, the video camera cannot deal with the sensor fixed at a different clock frequency; the video camera does not have sufficient versatility.